Saturday , October 23 2021

Single bit half adder with carry and enable using VHDL

Single bit half adder with carry and enable using VHDL

 

Specifications:

  • Inputs and outputs are each one bit
  • When enable is high, result gets x plus y
  • When enable is high, carry gets any carry of x plus y
  • Outputs are zero when enable input is low

Single bit half adder with carry and enable using VHDL

Step1:

Input and output ports are declared

\begin{array}{l}ENTITY\;half\_adder\;IS\;\;\;\;\;\\PORT(x,y,enable:IN\;bit;\\\;\;\;\;\;\;\;\;\;\;\;carry,result:OUT\;bit);\\END\;half\_adder;\end{array}

Step 2: Behavioral Specification 

\begin{array}{l}ARCHITECTURE\;half\_adder\_a\;of\;half\_adder\;IS\\\;BEGIN\\\;\;\;\;\;\;\;PROCESS\;(x,\;y,\;enable)\;\;\;\;\;\;\;\;\;\;\;\;\;\;\\\;\;\;\;\;\;\;\;\;BEGIN\\\;\;\;\;\;\;\;\;\;\;\;\;\;\;\;IF\;enable\;=\;‘1’\;THEN\;\\\;\;\;\;\;\;\;\;\;\;\;\;\;\;\;\;\;\;\;\;\;\;\;\;\;\;\;result\;<=\;x\;XOR\;y;\\\;\;\;\;\;\;\;\;\;\;\;\;\;\;\;\;\;\;\;\;\;\;\;\;\;carry\;<=\;x\;AND\;y;\\\;\;\;\;\;\;\;\;\;\;\;\;ELSE\\\;\;\;\;\;\;\;\;\;\;\;\;\;\;\;\;\;\;\;\;\;\;\;carry<=‘0’\\\;\;\;\;\;\;\;\;\;\;\;\;\;\;\;\;\;\;\;\;\;\;\;result<=‘0’\\\;\;\;\;\;\;\;\;\;\;\;END\;IF;\\\;\;\;\;\;\;END\;PROCESS;\\END\;half\_adder\_a;\end{array}

 

Step 3: Data Flow Specification 

\begin{array}{l}ARCHITECTURE\;half\_adder\_b\;of\;half\_adder\;IS\\\;\;\;\;\;BEGIN\\\;\;\;\;\;\;\;\;\;\;carry<=enable\;AND\;(x\;AND\;y);\\\;\;\;\;\;\;\;\;\;\;result<=enable\;AND\;(x\;XOR\;y);\\\;\;\;\;\;END\;half\_adder\_b;\end{array}

Step 4: Structural Specification

Single bit half adder with carry and enable using VHDL

 

Single bit half adder with carry and enable using VHDL

Read:What is VHDL and advantages of VHDL

Check Also

Explain body effects in MOS transistor

Explain body effects in MOS transistor?

Explain body effects in MOS transistor?   body effects in MOS transistor Normally, we considered …